Niobium Microsystems develops high-performance microelectronic technologies designed to securely collect, process, and distribute critical data. The company partners with U.S. Department of Defense and commercial clients who require advanced solutions that deliver improved efficiency, low power consumption, and strong security.

Founded in 2021 as a spinout from a leading security and computing systems R&D organization, Niobium Microsystems combines decades of expertise in semiconductor engineering and advanced cryptography. The company’s headquarters is located in Dayton, Ohio, with additional offices in Portland, Oregon, and Columbus, Ohio, while also supporting flexible work arrangements for qualified candidates regardless of location.

Position Overview

Niobium Microsystems is seeking an experienced RTL Design Engineer / SoC Engineer with at least 5 years of industry experience in semiconductor design. The successful candidate will join a highly skilled engineering team responsible for designing, verifying, and implementing advanced System-on-Chip (SoC) architectures.

In this role, you will contribute to the development of complex chip designs, from architecture and RTL implementation to verification and silicon bring-up.

Key Responsibilities

• Participate in architectural feasibility studies and system planning
  
  
• Develop micro-architecture specifications based on SoC design requirements
  
  
• Design, implement, and integrate complex SoC blocks
  
  
• Create block-level test cases to ensure functional and reliable designs
  
  
• Develop synthesis constraints and resolve timing issues
  
  
• Identify and fix issues related to Lint, CDC, and DFT
  
  
• Debug RTL and gate-level simulation failures at block and chip levels
  
  
• Assist with Engineering Change Orders (ECOs) and silicon bring-up processes
  
  

Required Skills and Experience

• Strong experience in RTL design using SystemVerilog or Verilog
  
  
• Experience integrating third-party IP components
  
  
• Knowledge of logic synthesis and static timing analysis
  
  
• Familiarity with SoC design flows, including chip-level and block-level design
  
  
• Experience modeling SoC architectures using FPGAs
  
  
• Understanding of industry bus protocols such as AXI, AMBA, or TileLink
  
  
• Experience with RISC-V architecture
  
  
• Familiarity with PCIe and DDR interfaces
  
  
• Knowledge of clock domain crossing (CDC) techniques
  
  
• Proficiency in scripting languages such as Python, Perl, Tcl, or Shell
  
  
• Experience using EDA tools for chip design and verification
  
  
• Strong debugging and problem-solving skills
  
  

Preferred Qualifications

• Experience with CHISEL-based SoC design
  
  
• Knowledge of asynchronous logic design methodologies
  
  

Benefits

• Competitive salary packages
  
  
• Employer-paid healthcare coverage
  
  
• Employer contributions to health savings accounts
  
  
• Flexible vacation and time-off policies
  
  
• Flexible work location with remote options
  
  
• 401(k) retirement plan with employer matching
  
  

Contact Information

📧 careers@niobiummicrosystems.com
 📍 444 E 2nd Street, Suite 250, Dayton, Ohio 45402
 🌐 https://niobiummicrosystems.com