RTL Design Engineer / SoC Engineer (Semiconductor & Chip Design Role)

Position Overview

Key Responsibilities

• Participate in architectural feasibility studies and system planning
  
  
• Develop micro-architecture specifications based on SoC design requirements
  
  
• Design, implement, and integrate complex SoC blocks
  
  
• Create block-level test cases to ensure functional and reliable designs
  
  
• Develop synthesis constraints and resolve timing issues
  
  
• Identify and fix issues related to Lint, CDC, and DFT
  
  
• Debug RTL and gate-level simulation failures at block and chip levels
  
  
• Assist with Engineering Change Orders (ECOs) and silicon bring-up processes
  
  

Required Skills and Experience

• Strong experience in RTL design using SystemVerilog or Verilog
  
  
• Experience integrating third-party IP components
  
  
• Knowledge of logic synthesis and static timing analysis
  
  
• Familiarity with SoC design flows, including chip-level and block-level design
  
  
• Experience modeling SoC architectures using FPGAs
  
  
• Understanding of industry bus protocols such as AXI, AMBA, or TileLink
  
  
• Experience with RISC-V architecture
  
  
• Familiarity with PCIe and DDR interfaces
  
  
• Knowledge of clock domain crossing (CDC) techniques
  
  
• Proficiency in scripting languages such as Python, Perl, Tcl, or Shell
  
  
• Experience using EDA tools for chip design and verification
  
  
• Strong debugging and problem-solving skills
  
  

Preferred Qualifications

• Experience with CHISEL-based SoC design
  
  
• Knowledge of asynchronous logic design methodologies
  
  

Benefits

• Competitive salary packages
  
  
• Employer-paid healthcare coverage
  
  
• Employer contributions to health savings accounts
  
  
• Flexible vacation and time-off policies
  
  
• Flexible work location with remote options
  
  
• 401(k) retirement plan with employer matching
  
  

Contact Information